1. Field of the Invention
This invention relates to electronic circuits and, more particularly, to pulse generation circuits that may be used in a current sense amplifier (ISA) for improving speed and robustness without compromising circuit stability or output swing.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Many semiconductor memories employ differential bit lines and some sort of differential amplifier or sensing circuit in their design. These differential amplifiers and sense circuits are commonly known as sense amplifiers (or “sense amps”). In addition to memory devices, sense amplifiers may be used in programmable arrays and other applications. A wide variety of sense amps are known in the art, including current sensing and voltage sensing variations.
For example, dynamic random access memory (DRAM) devices usually employ voltage sense amplifiers (VSAs) for detecting the state of a DRAM memory cell. In voltage sensing, the bitline is precharged before the memory cell is activated. When the memory cell is activated, the memory cell charges or discharges the bit line to maintain or change the voltage of the bit line. However, the bit line may be quite long and loaded by a large number of memory cells in some memory devices (e.g., large memory arrays), resulting in a large capacitive load for the memory cell. In some cases, the memory cell may not be able to provide enough cell current to quickly discharge or charge a large bit line, and an excessive amount of time may be needed to read the memory cells. Therefore, voltage sensing may not be the preferred sensing scheme in all memory devices.
For this reason, current sense amplifiers (ISAs) are sometimes used in memory device circuits. Because current sense amplifiers provide sensing speeds that are independent of the capacitive loads on the bit lines, they are well suited in large memory arrays that are subject to large loads on the bit lines. Located in a sense amplifier cell, the current sense amplifier measures a current and turns this into a small voltage difference output. In some cases, the output of a current sense amplifier may be passed to a voltage sense amplifier (VSA), which is also located in the sense amplifier cell for amplifying the low voltage signal into a higher voltage signal. The output of the voltage sense amplifier may then be passed as the output of the sense amplifier cell.
FIG. 1 illustrates one embodiment of a current sense amplifier 100, which may be used for detecting a current differential between the complementary bit lines of a memory array (such as memory array 150). In the embodiment shown, ISA 100 is coupled for receiving a pair of differential currents (IBL, IBLB) from one or more complementary bit lines (BL, BLB) of memory array 150. In some cases, ISA 100 may be coupled for receiving a pair of differential currents from only one column of memory cells, as shown in FIG. 1. In other cases, ISA 100 may be coupled for receiving a pair of differential currents from more than one column of memory cells (not shown). If the memory array includes more than one column of memory cells, column multiplexers (COLMUX) are generally used to switch between the different pairs of bit lines.
As shown in FIG. 1, current sense amplifier 100 may include a pair of PMOS cross-coupled transistors (M2a, M2b), a pair of PMOS load transistors (M3a, M3b), a pair of PMOS pull-up transistors (M4a, M4b) and an NMOS enable transistor (M5). When employed within a memory device, differential bit line currents (IBL, IBLB) may be supplied to the source terminals of cross-coupled transistors M2a and M2b during a read operation. To be “cross-coupled,” the gate terminal of PMOS transistor M2a must be coupled to the drain terminal of PMOS transistor M2b, and vice versa. The drain terminals of cross-coupled transistors M2a and M2b may then be coupled to ground through load transistors M3a, M3b and enable transistor M5. Pull-up transistors M4a and M4b are used for precharging the output nodes (out, out_b) of the current sense amplifier before the read (or “sense”) operation begins. Once the sense amplifier is enabled (e.g., when an active enable signal, “en,” is supplied to transistor M5), ISA 100 converts the pair of differential currents into a pair of differential voltages by allowing load transistors M3a, M3b to discharge the output nodes before a voltage difference is allowed to develop there between. In some cases, the pair of differential voltages may be supplied to a voltage sense amplifier (not shown). If used, the VSA may amplify the differential voltages (e.g., up to CMOS levels) and use the amplified voltages to generate a single-ended sense amplifier output voltage.
In FIG. 1, cross-coupled PMOS devices M2a and M2b provide a virtual short between the bit lines. This enables current from the memory cell to immediately begin flowing into the source terminals of these devices. This cross-coupled topology and the virtual short it creates makes the current sensing approach relatively insensitive to bit line loading, and hence, faster for large memory arrays as compared to conventional voltage sensing schemes.
The PMOS load devices (M3a and M3b) coupled below cross-coupled devices M2a and M2b serve two purposes. The first purpose is to convert the cell current into a voltage difference between output nodes out and out_b, which may then serve as inputs to a subsequent voltage sensing stage. The delay attributed to the current sensing stage may be described as the time it takes for the voltage difference to develop into a value, which is large enough for the voltage sensing stage to detect and amplify (e.g., the delay of the current sensing stage must account for input offsets of the voltage sensing stage with room for extra overdrive). The second purpose of the PMOS load devices (M3a and M3b) is to stabilize the current sense amplifier circuit. For example, if the resistance of load devices M3a and M3b is too low, a negative impedance may be created at the inputs of cross-coupled transistors M2a and M2b, which may cause the circuit to oscillate. Therefore, load devices M3a and M3b are generally required to have a large resistance in order to provide the desired signal swing and circuit stability.
However, a trade-off arises between load resistance and the delay of the current sensing stage. For example, when the bit lines are inactive, all nodes are precharged to a power supply voltage (vpwr) by the pull-up transistors (M1a and M1b) in the memory array and the pull-up transistors (M4a and M4b) in the ISA. Assuming that the memory array is initially disabled when the sense amp is enabled, nodes out and out_b (which are initially at vpwr) will start to discharge. The output node voltages will eventually settle to a maximum common mode value that is given by a voltage division between the resistances above and below the output nodes. Since the output node voltages started at vpwr, the output capacitance discharges through PMOS loads M3a and M3b with a common mode time constant, which is proportional to the PMOS load resistance. Once the output node voltages settle to the maximum common mode value, the memory cell current flows through the PMOS loads to create the voltage difference between output nodes out and out_b.
The tradeoff is that in order to satisfy the stability and voltage swing criteria listed above, the PMOS load resistances have to be made large. If the PMOS load resistances are made large, the common mode settling time of output nodes out and out_b is increased. This common mode settling delay directly adds to the delay of the current sensing stage. This is shown in FIG. 2, where the delay in reaching the maximum common mode voltage (before the output nodes begin to split) is almost 50% of the total delay of the current sensing stage (which is approximately 6 ns to 8 ns in FIG. 2). As used herein, the total delay of the current sensing stage is defined as the time needed for the difference in the out and out_b voltages to reach 100 mV. This number is based on the expected input offset voltage of the following voltage sensing stage.
Therefore, it would be desirable to provide a current sense amplifier scheme where speed is not compromised for stability or for developing the desired differential split between the output nodes.